As higher levels of integration are achieved, with the ultimate goal being a computer on a wafer or on a chip, all system functions are to be provided for on the same slice of silicon. The total integration of the diverse logic functions and of the diverse memory functions preferably is accomplished with a minimum of hardware and in such a manner that performance is not sacrificed. In this connection, it is advantageous to integrate a read/write memory array and a read only memory array into a single array chip in order to accomplish chip area savings over separate and independent arrays. One such integration technique is disclosed in U.S. Pat. No. 3,820,086, issued June 25, 1974 to Irving T. Ho et al, entitled "Read Only Memory (ROM) Superimposed on Read/Write Memory (RAM)" and assigned to the present assignee. Said patent discloses a memory array comprising dual mode memory cells wherein each cell is capable of simultaneously reading out the information contained in the cell by virtue of its read/write mode of operation as well as its read/only mode of operation. Although considerable memory area savings are realized by application of the aforesaid invention, the number of bits in the read/only memory cannot exceed the number of bits in the read/write memory. A need exists, however, for integrated memories where the number of read only bits substantially exceed the number of read/write bits.